Formal Verification – Is It Real Enough? - Technical Paper from DAC 2005
IBM
Paper by Yaron Wolfsthal and Rebecca M. Gott.
While Formal Verification (FV) of logic designs has been described in an industrial context for over a decade, it has not yet become a mainstream methodology. Our purpose in this report is to summarize a body of experience in the application of industrial-scale FV. We aim to present our insights and recommendations to practicing engineers and managers, who wish to evaluate the inclusion of FV as a part of their design methodology. In doing so, we hope to contribute to the understanding of the full potential of FV, based on our positive experience with this paradigm. We focus on providing practical information about the process of FV as possible within the limited scope of this text. Our analysis is based on observations and data collected from the application of over 100 projects across IBM and customers.
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